diff --git a/src/main/scala/CPU.scala b/src/main/scala/CPU.scala
index 51d1360..551f62c 100644
--- a/src/main/scala/CPU.scala
+++ b/src/main/scala/CPU.scala
@@ -136,5 +136,6 @@ class CPU extends MultiIOModule {
   IF.io.branchAddress := EXBarrier.out.ALUResult
 
   // Stall
-  IF.io.stall := ID.io.stall
+  IF.io.stall := IDBarrier.stall || ID.io.stall
+  IFBarrier.stall := IDBarrier.stall
 }
diff --git a/src/main/scala/ID.scala b/src/main/scala/ID.scala
index 7ea6e01..5627fe4 100644
--- a/src/main/scala/ID.scala
+++ b/src/main/scala/ID.scala
@@ -94,16 +94,12 @@ class InstructionDecode extends MultiIOModule {
     stallDelay,
     stallsRemaining - 1.U,
     Mux(
-      decoder.controlSignals.memRead,
-      1.U,
-      Mux(
-        decoder.controlSignals.branch,
-        3.U,
-        0.U
-      )
+      decoder.controlSignals.branch,
+      3.U,
+      0.U
     ))
 
-  val stall = stallsRemaining > 1.U || decoder.controlSignals.memRead && !stallDelay || decoder.controlSignals.branch && !stallDelay
+  val stall = stallsRemaining > 1.U || decoder.controlSignals.branch && !stallDelay
   io.stall :=  stall
 
   io.jump := Mux(stallDelay, false.B, decoder.controlSignals.jump)
diff --git a/src/main/scala/IDBarrier.scala b/src/main/scala/IDBarrier.scala
index 105ca34..c924233 100644
--- a/src/main/scala/IDBarrier.scala
+++ b/src/main/scala/IDBarrier.scala
@@ -27,9 +27,11 @@ class IDBarrier extends MultiIOModule {
     new Bundle {
       val in = Input(new IDBarrierIO)
       val out = Output(new IDBarrierIO)
+      val stall = Output(Bool())
     })
 
   val delay = Reg(new IDBarrierIO)
   delay := io.in
   io.out := delay
+  io.stall := io.out.memRead
 }
diff --git a/src/main/scala/IFBarrier.scala b/src/main/scala/IFBarrier.scala
index 0523874..755410b 100644
--- a/src/main/scala/IFBarrier.scala
+++ b/src/main/scala/IFBarrier.scala
@@ -10,11 +10,25 @@ class IFBarrier extends MultiIOModule {
       val PCout = Output(UInt(32.W))
       val instructionIn = Input(new Instruction)
       val instructionOut = Output(new Instruction)
+      val stall = Input(Bool())
     })
 
   val PC = RegInit(UInt(32.W), 0.U)
-  PC := io.PCin
+  PC := Mux(io.stall, PC, io.PCin)
   io.PCout := PC
 
-  io.instructionOut := io.instructionIn
+  val instruction = Reg(new Instruction)
+  val replay = RegInit(Bool(), false.B)
+  replay := io.stall
+  instruction := io.instructionIn
+
+  io.instructionOut := Mux(
+    io.stall,
+    Instruction.NOP,
+    Mux(
+      replay,
+      instruction,
+      io.instructionIn
+    )
+  )
 }
diff --git a/src/test/scala/Manifest.scala b/src/test/scala/Manifest.scala
index 01665d6..79d6989 100644
--- a/src/test/scala/Manifest.scala
+++ b/src/test/scala/Manifest.scala
@@ -19,7 +19,7 @@ import LogParser._
 
 object Manifest {
 
-  val singleTest = "fucked.s"
+  val singleTest = "simpleload.s"
 
   val nopPadded = false