diff --git a/src/main/scala/CPU.scala b/src/main/scala/CPU.scala
index 39e430e..69712e2 100644
--- a/src/main/scala/CPU.scala
+++ b/src/main/scala/CPU.scala
@@ -119,4 +119,7 @@ class CPU extends MultiIOModule {
   IDBarrier.forwardMemData := MEM.io.dataOut
   IDBarrier.forwardMem := EXBarrier.writeEnableOut
   IDBarrier.forwardMemAddr := EXBarrier.writeAddrOut
+
+  // Stall
+  IF.io.stall := ID.io.stall
 }
diff --git a/src/main/scala/ID.scala b/src/main/scala/ID.scala
index f54660e..8942aa8 100644
--- a/src/main/scala/ID.scala
+++ b/src/main/scala/ID.scala
@@ -39,6 +39,7 @@ class InstructionDecode extends MultiIOModule {
       val branchType = Output(UInt(3.W))
       val jump = Output(Bool())
       val returnAddr = Output(UInt(32.W))
+      val stall = Output(Bool())
     }
   )
 
@@ -84,13 +85,19 @@ class InstructionDecode extends MultiIOModule {
   io.r2Value := registers.io.readData2
   io.r2Address := registers.io.readAddress2
 
-  io.jump := decoder.controlSignals.jump
-  io.returnAddr := io.pc + 4.U
-
   io.ALUOp := decoder.ALUop
   io.branchType := decoder.branchType
   io.writeAddrOut := decoder.instruction.registerRd
-  io.writeEnableOut := decoder.controlSignals.regWrite
-  io.memRead := decoder.controlSignals.memRead
-  io.memWrite := decoder.controlSignals.memWrite
+
+  val stallDelay = RegInit(Bool(), false.B)
+  val stall = Mux(stallDelay, false.B, decoder.controlSignals.memRead)
+  io.stall :=  stall
+  stallDelay := stall
+
+  io.jump := Mux(stallDelay, false.B, decoder.controlSignals.jump)
+  io.returnAddr := io.pc + 4.U
+
+  io.writeEnableOut := Mux(stallDelay, false.B, decoder.controlSignals.regWrite)
+  io.memRead := Mux(stallDelay, false.B, decoder.controlSignals.memRead)
+  io.memWrite := Mux(stallDelay, false.B, decoder.controlSignals.memWrite)
 }
diff --git a/src/main/scala/IF.scala b/src/main/scala/IF.scala
index f35311e..35b0842 100644
--- a/src/main/scala/IF.scala
+++ b/src/main/scala/IF.scala
@@ -27,6 +27,7 @@ class InstructionFetch extends MultiIOModule {
       val instruction = Output(new Instruction)
       val branch = Input(Bool())
       val branchAddress = Input(UInt(32.W))
+      val stall = Input(Bool())
     })
 
   val IMEM = Module(new IMEM)
@@ -47,7 +48,7 @@ class InstructionFetch extends MultiIOModule {
     */
   io.PC := PC
   IMEM.io.instructionAddress := PC
-  PC := Mux(io.branch, io.branchAddress, PC + 4.U)
+  PC := Mux(io.stall, PC, Mux(io.branch, io.branchAddress, PC + 4.U))
 
   val instruction = Wire(new Instruction)
   instruction := IMEM.io.instruction.asTypeOf(new Instruction)
diff --git a/src/test/resources/tests/simpleload.s b/src/test/resources/tests/simpleload.s
new file mode 100644
index 0000000..e5396c2
--- /dev/null
+++ b/src/test/resources/tests/simpleload.s
@@ -0,0 +1,11 @@
+main:
+	addi x1, zero, 4
+	lw x1, 0(x1)
+	lw x1, 0(x1)
+	addi x1, zero, 4
+	done
+#memset 0x0,  4
+#memset 0x4,  8
+#memset 0x8,  12
+#memset 0xc,  16
+#memset 0x10, 20